Precise Interrupt Schemes for Pipelined Processors and a Recommendation for Virtual Memory Processor Systems

This paper describes and evaluates the results obtained in implementing three methods of precise interrupts in pipeline processors in-order instruction completion, the reorder buffer, and the reorder buffer with bypass paths. Due to the limited scope of this paper, two other methods of implementing precise interrupts the history buffer and future file are not investigated. An interrupt is defined as precise if all instructions before the program counter at the interrupt have finished execution and all instructions after the program counter at the interrupt have not modified the system. The importance of precise interrupts is obvious if an interrupt is precise, very little manipulation of the process state is required of the operating system before it services the interrupt, allowing for the interrupt to be transparent. If the interrupt is precise, resumption of the interrupted process is also a simple matter since the point of interruption of the process is readily evident. Based on simulation results, it will be shown that precise interrupts can be implemented via the methods to be discussed with as little as 3 % performance loss. From this data, it will then be demonstrated that these methods also allow for the implementation of precise interrupts in virtual memory with equivalent performance degradations, causing the support of page faults to be precise as well as transparent. I. Architecture The model architecture used in [2] is registerregister where all memory accesses and functional operations involve registers. Load instructions require the computation of an effective address that is the effective address equals the register value plus an offset displacement, and are of the form Ri = (Rj + disp) where the contents of the memory location are loaded into Ri. The store operates in the same manner, and is of the form (Rj + disp) = Ri. That is, the contents of Ri are stored in memory location Rj + displacement. Functional instructions are of the form Ri = Rj op Rk. A more detailed description of the architecture can be found in [2]. The following assumptions are made about the architecture of [2]. In order to facilitate the handling of interrupts that occur prior to instruction issue, it is assumed that instructions remain in sequence until issued. Of greater import is that the process state remains unmodified by an instruction prior to its issue. Therefore when an interrupt is detected prior to instruction issue, a halt occurs leaving the process in a precise state. This allows for simple restart of the process and is of a trivial nature when the precise interrupt issue is examined. This paper will concentrate on interrupts detected after instruction issue. II. In-Order Instruction Completion This method requires that instructions do not modify the process state unless all previously issued instructions have been found to be exception free. To control the result bus of the architecture in [2], a result shift register (RSHR) is used and operates as follows. When an interrupt occurs, the process is halted and a window of instructions is examined. The instructions in this window are reissued to precisely determine where the interrupt occurred. Let the window of instructions under consideration to be I1 through In whose order is known based on the program counter value for each instruction. Each instruction's time of execution is also known, and based on this time of execution, a stage is reserved in the RSHR. Therefore if instruction Ij has execution time t1 and instruction Ii+1 has execution time t2 with t2>t1, then instruction Ii reserves stage t1 in the RSHR and instruction Ii+1 reserves stage t2 in the RSHR. Each clock cycle shifts the stage up one location in the RSHR until it is shifted out of the RSHR representing completion. However, if instruction Ij has execution time t1 and instruction Ii+1 has execution time t2 with t1>t2, instruction Ii is placed in stage t1 of the RSHR but instruction Ii+1 must wait until instruction Ii has been shifted up passed stage t2 in the RSHR before it is placed in stage t2 of the RSHR. When a stage is filled with an instruction in the RSHR, the valid bit is set to denote the fact that the stage is no longer empty. The destination register tag is also maintained in the stage of the RSHR so that the result bus is controlled and routed to that register when an instruction reaches stage one of the RSHR. This guarantees in-order execution of the instructions. If an instruction completes out of the RSHR and an exception is detected, then this instruction is known to be the one that caused the interrupt. Thus the interrupt is now precise and the proper process state may be saved while the interrupt is serviced and the process restarted at the proper point upon completion of servicing of the interrupt. Figure 2 from [2] is reproduced here to illustrate the RSHR with the direction of movement being from stage N towards stage 1. STAGE FUNCTIONAL UNIT SOURCE DESTN REGISTER VALID PROGRAM COUNTER